Publications

Patent Applications
  1. (WP1 / IHP/ ESR1.2) ​Junchao Chen,  Milos Krstic, Marko Andjelkovic, Aleksandar Simevski, “Electronic Circuit With Integrated SEU Monitor”，European Patent Application, EP 3748637, 09.12.2020 Bulletin 2020/50, [open access]

Scientific publications
  1. (WP1 / TUD / ESR1.1) G. Medeiros, L. Bolzani Poehls, M. Taouil, F. Luis Vargas, S. Hamdioui, “A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs,” in Microelectronics Reliability, Elsevier, vol. 88-90, pp. 355–359, September 2018. [doi] [url] (open access)
  2. (WP1 / PDT / ESR1.4) B. Du, J. E. Rodriguez Condia, M. Sonza Reorda and L. Sterpone, "About the functional test of the GPGPU scheduler," 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Platja D'Aro, Spain, 2018, pp. 85-90. [doi] [url] [open access]
  3. (WP1 / PDT / ESR1.4) B. Du, J. E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone, “In-Field GPGPU Test with SBST Techniques”, NVIDIA's GPU Technology Conference (GTC) Europe 2018, Munich, Germany, October 9-11, 2018. [url] [doi] [open access]
  4. (WP1 / PDT / ESR1.4) J. E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone, “On the functional test of the GPGPU scheduler”, A workshop on Self-driving Cars and Reliability, Rutherford Appleton Laboratory, Harwell Campus, UK, 31st May - 1st June 2018. [doi] [url] [open access]
  5. (WP1 / iROC / ESR1.5) T. Lange, M. Glorieux, A. Evans, A-D. In, D. Alexandrescu, C. Boatella-Polo, C. Urbina Ortega, V. Ferlet-Cavrois, M. Tali, R. Garcı́a Alı́a, “Single Event Characterization of a Xilinx  UltraScale+ MP-SoC FPGA,” 2018 ESA/ESTEC Space FPGA Users Workshop (SEFUW’18). [doi] [url] [open access]
  6. (WP1 / iROC, PDT / ESR1.5) L. Sterpone, S. Azimi, L. Bozzoli, B. Du, T. Lange, M. Glorieux, D. Alexandrescu, C. Boatella Polo, D. Merodio Codinachs, "A Novel Error Rate Estimation Approach for UltraScale+ SRAM-based FPGAs," 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, United Kingdom, 2018, pp. 120-126. [doi] [open access]
  7. (WP1 / iROC / ESR1.5) M. Glorieux, A. Evans, T. Lange, A-Duong In, D. Alexandrescu, C. Boatella-Polo, R. Garcı́a Alı́a, M. Tali, C. Urbina Ortega, M. Kastriotou, P. Fernández-Martı́nez, and V. Ferlet-Cavrois, "Single-Event Characterization of Xilinx UltraScale+® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation," 2018 IEEE Radiation Effects Data Workshop (REDW), Waikoloa Village, HI, 2018, pp. 1-5. [doi] [open access]
  8. (WP2 / PDT / ESR2.1) R. Cantoro, A. Damljanovic, M. Sonza Reorda and G. Squillero, "A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks,“ IEEE Int. Test Conference in Asia (ITC-Asia), Harbin, China, 2018, pp. 55-60. (Best paper award!) [doi] [open access]
  9. (WP2 / PDT / ESR2.1) R. Cantoro, A. Damljanovic, M. Sonza Reorda and G. Squillero, "A New Technique to Generate Test Sequences for Reconfigurable Scan Networks," 2018 IEEE International Test Conference (ITC), Phoenix, AZ, USA, 2018, pp. 1-9., [doi] [open access]
  10. (WP2 / PDT / ESR2.1) R. Cantoro, A. Damljanovic, M. Sonza Reorda and G. Squillero, "Comparing different approaches to the test of Reconfigurable Scan Networks," 2018 3rd International Test Standards Application Workshop (TESTA) [url] [open access]
  11. (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka, P. Langendörfer. “Fault Injections: Most Often Used Setups,” in 29. Krypto-Tag, Renningen, September 6-7, 2018 [doi] [open access]
  12. (WP4 / CDNS / ESR4.1) F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer, "Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262," 2018 Design and Verification Conference and Exhibition (DVCon) Europe, Munich, Germany, 2018. [doi] [url] [gold open access]
  13. (WP4 / CDNS / ESR4.2) A. C. Bagbaba, F. Augusto da Silva, C. Sauer, "Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262," 2018 Design and Verification Conference and Exhibition (DVCon) Europe, Munich, Germany, 2018. [doi] [url] [open access]
  14. (WP2 / TUT / ESR2.4) M. Jenihhin, X. Lai, T. Ghasempouri, J. Raik, “Towards Multidimensional Verification: Where Functional Meets Non-Functional,” IEEE NorCAS Conference, Tallinn, October 2018, pp 1-6. [doi] [open access]
  15. (WP5 / BTU, TUT, PDT / -) H. T. Vierhaus, M. Jenihhin and M. Sonza Reorda, “RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality,” 12th IEEE EWME, Braunschweig, 2018, pp. 1-6. [doi] [open access]
  16. (WP2 / TUT / ESR4.3) A. S. Oyeniran, R. Ubar, M. Jenihhin, C. C. Gürsoy and J. Raik, "Mixed-level identification of fault redundancy in microprocessors," 2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile, 2019, pp. 1-6. [doi] [open access]
  17. (WP1 / TUT / ESR4.3)  D. H. P. Kraak, C. C. Gürsoy, I.O. Agbo, M. Taouil, M. Jenihhin, J. Raik and S. Hamdioui, "Software-Based Mitigation for Memory Address Decoder Aging," 2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile, 2019, pp. 1-6. [doi] [open access]
  18. (WP1 / PDT / ESR1.4) B. Du, J. E. Rodriguez Condia, M. Sonza Reorda and L. Sterpone, "On the evaluation of SEU effects in GPGPUs," 2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile, 2019, pp. 1-6. [doi] [open access]
  19. (WP1 / TUD / ESR1.1) G. C. Medeiros, M. Taouil, M. Fieback, L. B. Poehls and S. Hamdioui, "DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs," 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 2019, pp. 1-2. [doi] [open access]
  20. (WP2, WP4 / TUT / ESR4.3) A. S. Oyeniran, R. Ubar, M. Jenihhin, C. C. Gürsoy and J. Raik, "High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors," 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 2019, pp. 1-6.[doi] [open access]
  21. (WP2 / PDT / ESR2.1) A. Damljanovic, A. Jutman, G. Squillero and A. Tsertov, "Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks," 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 2019, pp. 1-6. [doi] [open access]
  22. (WP2 / PDT / ESR2.1) R. Cantoro, A. Damljanovic, M. Sonza Reorda and G. Squillero, "An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests”, 2019, Journal of Circuits," Systems and Computers Vol. 28, No.1 [doi] [open access]
  23. (WP1 / PDT / ESR1.4) J. E. Rodriguez Condia, M. Sonza Reorda, "An extended GPGPU model to support detailed reliability analysis," SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, 27-28 March 2019 [doi] [url] [open access]
  24. (WP1 / iROC, PDT / ESR1.5, ESR2.3) T. Lange, A. Balakrishnan, M. Glorieux, D. Alexandrescu, L. Sterpone, "Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits," SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, 27-28 March 2019 [doi] [url] [open access]
  25. (ALL / ALL / ALL) C. C. Gürsoy, G. Medeiros, J. Chen, N. George, J. E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. Augusto da Silva, A. Bagbaba, S.Hamdioui, M.Taouil, M.Krstic, P.Langendörfer, Z.Dyka, M.Huebner, J.Nolte, H.T.Vierhaus, M.Sonza Reorda, G.Squillero, L.Sterpone, J.Raik, D.Alexandrescu, M.Glorieux, G.Selimis, G.J.Schrijen, A.Klotz, C.Sauer, M.Jenihhin, "RESCUE EDA Toolset for Interdependent Aspects of Reliability, Security and Quality in Nanoelectronic Systems Design," University Booth, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy [doi] [url1] [url2] [gold open access] [open access]
  26. (WP2 / TUT, PDT / ESR4.3) C. C. Gürsoy, M. Jenihhin, A.S. Oyeniran, D. Piumatti, J. Raik, M. Sonza Reorda, R. Ubar, "New categories of Safe Faults in a processor-based Embedded System," 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania, 2019, pp. 1-4. [doi] [open access]
  27. (WP3, WP2 / TUT / ESR2.4) X. Lai, M. Jenihhin, J. Raik and K. Paul, "PASCAL: Timing SCA Resistant Design and Verification Flow," 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, 2019, pp. 239-242. [doi][open access]
  28. (WP2 / TUT, iROC / ESR2.4, ESR2.3, ESR1.5) X. Lai, A. Balakrishnan, T. Lange, M. Jenihhin, T. Ghasempouri, J. Raik, D. Alexandrescu, “Understanding multidimensional verification: Where functional meets non-functional,” Microprocessors and Microsystems, Volume 71, 2019, 102867, ISSN 0141-9331, [doi] [gold open access]
  29. (WP1 / PDT, TUT / ESR2.1, ESR4.3) A. Damljanovic, G. Squillero, C. C. Güursoy and M. Jenihhin, "On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks," 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), Cuzco, Peru, 2019, pp. 335-340. [doi] [open access]
  30. (WP2, WP1 / TUT, iROC, PDT / ESR2.3) M. Jenihhin, M. S. Reorda, A. Balakrishnan and D. Alexandrescu, "Challenges of Reliability Assessment and Enhancement in Autonomous Systems," 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Noordwijk, Netherlands, 2019, pp. 1-6. [doi] [open access]
  31. (WP1 / IHP / ESR1.2) J. Chen, M. Andjelkovic, A. Simevski, Y. Li, P. Skoncej and M. Krstic, "Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems," 2019 22nd Euromicro Conference on Digital System Design (DSD), Kallithea, Greece, 2019, pp. 514-521. [doi] [url] [open access]
  32. (WP1 / PDT / ESR1.4) B. Du, J. E. Rodriguez Condia and M. Sonza Reorda, "An extended model to support detailed GPGPU reliability analysis," 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Mykonos, Greece, 2019, pp. 1-6. [doi] [open access]
  33. (WP1 / PDT / ESR1.4) S. d. Carlo, J. E. Rodriguez Condia and M. Sonza Reorda, "On the in-field test of the GPGPU scheduler memory," 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania, 2019, pp. 1-6. [doi] [open access]
  34. (WP1 / PDT / ESR1.4) J. E. Rodriguez Condia and M. Sonza Reorda, "Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach," 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, 2019, pp. 97-102. [doi] [open access]
  35. (WP1 / PDT / ESR1.4) B. Du; J. E. Rodriguez Condia; M. Sonza Reorda; L. Sterpone, "An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects," 30th European Conference on Radiation and its Effects on Components and Systems (RADECS), Montpellier, France, September 16-20th, 2019 [doi] [open access]
  36. (WP1 / PDT / ESR1.4) S. Di Carlo, J. E. Rodriguez Condia and M. Sonza Reorda, "An on-line testing technique for the scheduler memory of a GPGPU," in IEEE Access. vol. 8, pp. 16893-16912. 2020, [doi] [url] [gold open access]
  37. (WP2 / PDT / ESR2.1) Damljanovic, A. Ruospo, E. Sanchez, G. Squillero, “A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores”, IEEE 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Vienna, Austria, 2021 [open access]
  38. (WP1, WP2 / CDNS, TUT / ESR4.2) C. Bagbaba, M. Jenihhin, J. Raik, C. Sauer, “Efficient Fault Injection based on Dynamic HDL Slicing Technique,” 2019 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, July 1 – 3, 2019. [doi] [open access]
  39. (WP4, WP2 / CDNS, TUD / ESR4.1, ESR4.2) F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer, "Efficient Methodology for ISO26262 Functional Safety Verification," 2019 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, July 1 – 3, 2019. [doi] [open access]
  40. (WP4, WP2 / CDNS, TUT / ESR4.2) C. Bagbaba, M. Jenihhin, J. Raik and C. Sauer, "Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing," IEEE Nordic Circuits and Systems Conference (NorCAS), Helsinki, Finland, October 29-30, 2019 [doi] [open access]
  41. (WP2 / BTU/ ESR2.2) R. Segabinazzi Ferreira and J. Nolte, “Low latency reconfiguration mechanism for fine-grained processor internal functional units,” in LATS 2019 - 20th IEEE Latin American Test Symposium, 2019 [doi] [open access]
  42. (WP1,WP2 / BTU, IHP / ESR2.2, ESR1.3, ESR1.2) R. Segabinazzi Ferreira, N. George, J. Chen, M. Hübner, M. Krstic, J. Nolte, and H. T. Vierhaus, “Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness,” in 2019 22nd Euromicro Conference on Digital System Design (DSD) (Work in Progress Session), 2019. [doi] [open access]
  43. (WP1/ iROC / ESR1.5) T. Lange, M. Glorieux, D. Alexandrescu, and L. Sterpone, "Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks," in 2019 14th International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS) [doi] [open access]
  44. (WP1 / iROC, PDT / ESR1.5, ESR2.3) T. Lange, A. Balakrishnan, M. Glorieux, D. Alexandrescu, and L. Sterpone, "On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques," in 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume (DSN-S) [doi] [open access]
  45. (WP1, WP2 / iROC, TUT / ESR2.3, ESR1.5) A. Balakrishnan, T. Lange, M. Glorieux, D. Alexandrescu and M. Jenihhin. ”Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors,” in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019. [doi] [open access]
  46. (WP1/ iROC, PDT / ESR1.5, ESR2.3) T. Lange, A. Balakrishnan, D. Alexandrescu, M. Glorieux, and L. Sterpone, "Machine Learning To Tackle the Challenges of Transient and Soft Errors in Complex Circuits," in 2019 IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS). [doi] [open access]
  47. (WP2 / iROC, TUT / ESR2.3, ESR1.5) A. Balakrishnan, T. Lange, M. Glorieux, D. Alexandrescu and M. Jenihhin , “The Validation of Graph Model Based Low-Dimensional Relevant Features of Gate-level Abstraction for Machine Learning Applications,” in  IEEE Nordic Circuits and Systems Conference (NorCAS), 2019. [doi] [open access]
  48. (WP1 / IHP / ESR1.2) M. Andjelkovic, M. Veleski, J. Chen, A. Simevski, M. Krstic, "A Particle Detector Based on Pulse Stretching Inverter Chain," Proc. 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019) [doi] [open access]
  49. (WP1 / PDT, CDNS / ESR1.4, ESR4.1) J. E. Rodriguez Condia; F. Augusto Da Silva; S. Hamdioui; C. Sauer and M. Sonza Reorda, "Untestable faults identification in GPGPUs for safety-critical applications," 26th IEEE International Conference on Electronics Circuits and Systems (ICECS 2019). [doi] [open access]
  50. (WP2 / PDT / ESR2.1) A. Damljanovic, A. Jutman, M. Portolan, E. Sanchez, G. Squillero, A. Tsertov, “Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL,” ITC 2019. [doi] [open access]
  51. (WP4, WP2 / CDNS, TUD / ESR4.1, ESR4.2) F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer, "Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification," IEEE Asia Test Symposium (ATS), Kolkata, India, December 10 – 19, 2019. [doi] [open access]
  52. (ALL / ALL / - supervisors) M. Jenihhin, S. Hamdioui, M. Sonza Reorda, M. Krstic, P. Langendoerfer, C. Sauer, A. Klotz, M. Huebner, J. Nolte, H. T. Vierhaus, G. Selimis, D. Alexandrescu, M. Taouil, G.-J. Schrijen, J. Raik, L. Sterpone, G. Squillero and Z. Dyka, "RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems," 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2020, pp. 1-6 [doi] [url] [open access]
  53. (WP1 / IHP, IROC/ ESR1.2, ESR1.5) ​J. Chen, T. Lange, Marko Andjelkovic, Aleksandar Simevski, Milos Krstic, “Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning”，Microelectronics Reliability, Volume 114, 2020, 113799, ISSN 0026-2714. [doi] [gold open access]
  54. (WP1 / IHP / ESR1.2) L. Yuanqing, A. Breitenreiter, M. Andjelkovic, J. Chen, M. Babic, M. Krstic, "Double cell upsets mitigation through triple modular redundancy," in Microelectronics Journal. Elsevier, vol. 96, 2020, Art. 104683 [doi] [open access]
  55. (WP2 / BTU/ ESR2.2) R. Rotta, R. Segabinazzi Ferreira and J. Nolte, "Real-Time Dynamic  Hardware Reconfiguration for Processors with Redundant Functional Units," 2020 IEEE 23rd International Symposium on Real-Time  Distributed Computing (ISORC), Nashville, TN, USA, 2020, pp. 154-155, [doi][open access]
  56. (WP2 / BTU/ ESR2.2, ESR1.3) R. Segabinazzi Ferreira, J. Nolte, F. Vargas, N. George and M. Hübner, "Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications," 2020 IEEE Latin-American Test Symposium (LATS), Maceio, Brazil, 2020, pp. 1-6, [doi] [open access]
  57. (WP4/CDNS/ESR4.1, ESR4.2) F. Augusto da Silva, A. C. Bagbaba, S. Sartoni, R. Cantoro, M. Sonza Reorda, S. Hamdioui, C. Sauer, "Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs," 2020 IEEE European Test Symposium (ETS), Tallinn, Estonia, July 2, 2020 [doi] [open access]
  58. (WP3 / TUT / ESR2.4) X. Lai, M. Jenihhin, G. Selimis, S. Goossens, R. Maes, K. Paul, “Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices”. IFIP/IEEE International Conference on Very LargeScale Integration 2020", [doi] [URL] [open access]
  59. (WP4 / CDNS / ESR4.1). F. Augusto da Silva, A. Cagri Bagbaba, A. Ruospo, R. Mariani, G. Kanawati, E. Sanchez, M Sonza Reorda, M. Jenihhin, S. Hamdioui, C. Sauer, "Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks". 2020 IEEE 38th VLSI Test Symposium (VTS): Proceedings, 2020, San Diego, United States, [doi] [open access]
  60. (WP1 / PDT / ESR1.4), Marcio M. Goncalves; Jose Rodrigo Azambuja; Josie E. Rodriguez Condia; Matteo Sonza Reorda and Luca Sterpone, " Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU," 21th IEEE Latin American Test Symposium (LATS 2020), [doi] [URL] [open access]
  61. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; P. Narducci; M. Sonza Reorda and L. Sterpone, "A dynamic reconfiguration mechanism to increase the reliability of GPGPUs," IEEE 38th VLSI Test Symposium (VTS2020), [doi] [URL] [open access]
  62. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; P. Narducci; M. Sonza Reorda and L. Sterpone," A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs," 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2020), [doi] [URL] [open access]
  63. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; M. M. Goncalves; J. R. Azambuja; M. Sonza Reorda and L. Sterpone," Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets," IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2020), [doi] [URL] [open access] 
  64. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia and M. Sonza Reorda," On the testing of special memories in GPGPUs," IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), [doi] [URL] [open access]
  65. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia and M. Sonza Reorda," Testing the divergence stack memory on GPGPUs: A modular in-field test strategy," 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2020), [doi] [URL] [open access]
  66. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; J-D. Guerrero-Balaguera; C-F. Moreno-Manrique and M. Sonza Reorda," Design and Verification of an open-source SFU model for GPGPUs," 17th Biennial Conference on Electronics and Embedded Systems (BECS2020), [doi] [URL] [open access]
  67. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; Boyang Du, M. Sonza Reorda and L. Sterpone," FlexGripPlus: An improved GPGPU model to support reliability analysis," in Microelectronics Reliability, Elsevier, Volume 109, June 2020, 113660, [doi] [URL] [Golden open access]
  68. (WP1 / PDT / ESR1.4), M. M. Goncalves; Josie E. Rodriguez Condia; M. Sonza Reorda, L. Sterpone and J. R. Azambuja," Improving GPU Register File Reliability with a comprehensive ISA extension," in Microelectronics Reliability, Elsevier, Volume 114, November 2020, 113768, [doi] [URL] [open access]
  69. (WP1 / PDT / ESR1.4), M. M. Goncalves; Josie E. Rodriguez Condia; M. Sonza Reorda, L. Sterpone and J. R. Azambuja," Improving GPU Register File Reliability with a comprehensive ISA extension," 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF2020), [doi] [URL] [open access]
  70. (WP1 / PDT / ESR1.4), A. Bosio; S. Di Carlo; G. Di Natale; M. Sonza Reorda and Josie E. Rodriguez Condia," Design techniques to improve the resilience of computing systems: software layer," in Cross-Layer Reliability of Computing Systems (2020), [doi] [open access]
  71. (WP1 / IHP, IROC/ ESR1.2, ESR1.5) ​J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic, "Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction," 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Frascati, Italy, 2020, pp. 1-6. [doi] [URL] [open access]
  72. (WP1 / IHP/ ESR1.2) M. Andjelkovic, A. Simevski, J. Chen,  M. Krstic, et al., "Design of Radiation Hardened RADFET Readout System for Space Applications," 2020 23rd Euromicro Conference on Digital System Design (DSD), Kranj, Slovenia, 2020, pp. 484-488. [doi] [URL] [open access]
  73. (WP1 / IHP/ ESR1.2) M. Andjelkovic, J. Chen, A. Simevski, Z. Stamenkovic, M. Krstic, R. Kraemer.“Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters”, Proc. 31st European Conference on Radiation and its Effects on Components and Systems (RADECS 2020). [open access]
  74. (WP1 / IHP/ ESR1.2) M. Andjelkovic, J. Chen, A. Simevski, Z. Stamenkovic, M. Krstic and R. Kraemer, "A Review of Particle Detectors for Space-Borne Self-Adaptive Fault-Tolerant Systems," 2020 IEEE East-West Design & Test Symposium (EWDTS), Varna, Bulgaria, 2020, pp. 1-8, [doi] [URL] [open access]
  75. (WP2,WP1/IROC/ESR2.3, ESR1.5) D. Alexandrescu; A. Balakrishnan; T. Lange; M. Glorieux (2020). "Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models". 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS): 26th International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 1−6. [doi] [URL] [open access]
  76. (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka and P. Langendörfer, "Sensitivity of Standard Library Cells to Optical Fault Injection Attacks in IHP 250 nm Technology," 2020 9th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, June 8 – 11, 2020, pp. 1-4. [doi] [URL] [open access]
  77. (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka, E. Perez, M. K. Mahadevaiaha, I. Kabin, Ch. Wenger and P. Langendörfer, “Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks”, 2020 23rd Euromicro Conference on Digital System Design (DSD), Kranj, Slovenia, August 26 - 28 2020, pp. 238-245. [doi] [URL] [open access]
  78. (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka, J. Katzer and P. Langendörfer, “Metal Fillers as Potential Low Cost Countermeasure against Optical Fault Injection Attacks”, 2020 IEEE East-West Design & Test Symposium (EWDTS), Varna, Bulgaria, September 4 – 7, 2020, pp. 1-6. [doi] [URL] [open access]
  79. (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka, P. Langendörfer, “Laser Fault Injection Attacks against IHP Chips”, in 32. Krypto-Tag, 1st Digital Summit, Germany, January 15, 2021. [doi] [URL] [open access]
  80. (WP3 / TUD / ESR3.3) T. Koylu, C. R. W. Reinbrecht, S. Hamdioui, M. Taouil, "RNN-Based Detection of Fault Attacks on RSA," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5. [doi] [open access]
  81. (WP4/ CDNS / ESR4.2) A. C. Bagbaba, M. Jenihhin, R. Ubar and C. Sauer, "Representing Gate-Level SET Faults by Multiple SEU Faults at RTL," 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Napoli, Italy, 2020, pp. 1-6. [doi] [URL] [open access]
  82. (WP1 / TUD,TUT / ESR1.1, ESR4.3) G. C. Medeiros, C. Cem Gürsoy, L. Wu, M. Fieback, M. Jenihhin, M. Taouil, S. Hamdiou, "A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs," 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2020, pp. 792-797. [doi] [URL] [open access] 
  83. (WP1 / TUD / ESR1.1) T. Copetti, G. C. Medeiros, M. Taouil, S. Hamdioui, L. B. Poehls and T. Balen, "Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects," 2020 IEEE Latin-American Test Symposium (LATS), Maceio, Brazil, 2020, pp. 1-6. [doi] [URL] [open access]
  84. (WP1/TUD /ESR1.1) G. C. Medeiros, M. Fieback, M. Taouil, L. B. Poehls, and S. Hamdioui, "Detecting Random Read Faults to Reduce Test Escapes in FinFETSRAMs," in2021 IEEE Eur. Test Symp. (ETS), May 2021 [open access].
  85. (WP3 / IID / ESR3.1) S. Masoumian, G. Selimis, R. Maes, G. Schrijen, S. Hamdioui and M. Taouil, "Modeling Static Noise Margin for FinFET based SRAM PUFs," 2020 IEEE European Test Symposium (ETS), Tallinn, Estonia, 2020, pp. 1-6. [doi] [URL][open access]
  86. (All / All / All) C.C. Gursoy, G. Medeiros, J. Chen, N. George, J.E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S.Hamdioui, M.Taouil, M.Krstic, P.Langend ̈orfer, Z.Dyka, M.Brandalero, M.H ̈ubner, J.N ̈olte, H.T.Vierhaus, M.Sonza Reorda, G.Squillero, L.Sterpone, J.Raik, D.Alexandrescu, M.Glorieux, G.Selimis, G.J.Schrijen, A.Klotz, C.Sauer and M.Jenihhin, “RESCUED: A Rescue Demonstrator for Interdependent Aspects of Reliability, Security and Quality Towards a Complete EDA Flow”, as a University Booth Exhibition Demo and Poster in 2020 Design, Automation and Test in Europe Conference (DATE 2020), as a Virtual Conference and Exhibition, 21 April – 30 June 2020. [doi] [url] [open access]
  87. (WP1,WP2/IROC/ESR1.5, ESR2.3) Lange T.; Balakrishnan A.; Glorieux M.; Alexandrescu D.; Sterpone L. (2020). Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS): 26th International Symposium on On-Line Testing and Robust System Design (IOLTS). [doi] [URL] [open access]
  88. (WP1,WP2/IROC/ESR1.5, ESR2.3) T. Lange; A. Balakrishnan; M. Glorieux; D. Alexandrescu; L. Sterpone (2020). Towards the Use of Machine Learning to Estimate the Functional Failure Rate of Complex Circuits. 2020 Single Event Effects Symposium and Military and Aerospace Programmable Logic Devices Workshop (SEE/MAPLD) (workshop publication).
  89. (WP1/IROC/ESR1.5) T. Lange; M. Glorieux; D. Alexandrescu; L. Sterpone (2020). Error Rate Calculation of Functional Failures Induced by Single-Event Transients in Clock Distribution Networks. 2020 Single Event Effects Symposium and Military and Aerospace Programmable Logic Devices Workshop (SEE/MAPLD). (workshop publication).
  90. (WP1 / PDT / ESR1.4), Josie E. Rodriguez Condia; P. Narducci; M. Sonza Reorda and L. Sterpone, "DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability," The Journal of Supercomputing (2021), 29 March 2021 [doi] [Gold Open Access]

 

Post-RESCUE Publications

  1. (WP2,WP1/IROC/ESR2.3, ESR1.5)  A. Balakrishnan, D. Alexandrescu and M. Jenihhin, T. Lange, and M. Glorieux (2021). "Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis." [doi] [in press!]
  2. (WP1/TUD /ESR1.1)  G. C. Medeiros, M. Fieback, L. Wu, M. Taouil, L. B. Poehls, and S. Hamdioui, “Hard-to-Detect Fault Analysis in FinFET SRAMs,” in IEEE Transactions on IEEE Transactions on Very Large Scale Integration Systems  (TVLSI), 2021 (in press!)



RESCUE Events

BELAS 2018 - PhD Forum:

  • (WP1 / TUD / ESR1.1) Guilherme Medeiros, Mottaqiallah Taouil, Said Hamdioui, "Unique FinFET Manufacturing Defects", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP1 / IHP / ESR1.2) J. Chen, M. Krstic, “Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems” Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia. [URL] [PDF] – Gold Open Access
  • (WP3 / BTU / ESR1.3) Nevin George, Petr Pfeifer, Heinrich T. Vierhaus, "Robust Detection and Correction of Delay Faults and Transient Faults", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP1 / PDT / ESR1.4) Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone "About the functional test of the GPGPU scheduler", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP1 / IROC / ESR1.5) Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, "Soft-Error Rate Due to Single-Event Transients in Clock Distribution Networks", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia. [PDF] – Gold Open Access
  • (WP2 / PDT / ESR2.1) R. Cantoro, A. Damljanovic, M. Sonza Reorda, G. Squillero, "Comparing different approaches to the test of IEEE 1687 reconfigurable scan networks", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP2 / BTU / ESR2.2) Raphael Segabinazzi Ferreira, Jörg Nolte, Nevin George, Heinrich T. Vierhaus"A fine-grained HW/SW co-supervisor running under dependable OS – The Concept", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP2 / IROC / ESR2.3) Aneesh Balakrishnan, "Application of Graph Neural Network for Estimating Probabilistic Inferences in the Combinational Circuits", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia. [PDF] – Gold Open Access
  • (WP2 / TUT / ESR2.4) Xinhui Lai, Maksim Jenihhin, Tara Ghasempouri, Apneet Kaur, Jaan Raik, "Towards Multidimensional Verification: Where Functional Meets Non-Functional"
  • (WP3 / IID / ESR3.1) Shayesteh Masoumian, Georgios Selimis, Roel Maes, Geert-Jan Schrijen, Said Hamdioui, "Study of SRAM-Physical Unclonable Function in FinFET and FD-SOI", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP3 / IHP / ESR3.2) D. Petryk, Z. Dyka, P. Langendörfer “Optical Fault Injections: a Setup Comparison” Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia. [PDF] – Gold Open Access
  • (WP3 / TUD / ESR3.3) Troya Koylu, Mottaqiallah Taouil, Said Hamdioui, "Intelligent System Design for Security Integration of Artificial Intelligence Security Modules in Hardware", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP4 / CDNS,TUD / ESR4.1,ESR4.2) Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer, "Exploring Formal Methods for verification of Fault Lists", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP4 / CDNS,TUT / ESR4.2,ESR4.1) Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, Maksim Jenihhin, Christian Sauer, "Improving the Confidence Level in Functional Safety Simulator Tools for ISO 26262", Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.
  • (WP4 / TUT / ESR4.3) Cemil Cem Gürsoy, “Open-Source EDA Tools for Design Quality and Reliability Automation Using zamiaCAD”, Proc. PhD Forum of the 8th BELAS Summer School, Tallinn, June 20 - 22, 2018, Estonia.

BELAS 2019 - PhD Forum:

  • (WP1 / TUD / ESR1.1) Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, “DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs”, Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • (WP1 / IHP / ESR1.2) Junchao Chen, Milos Krstic, “Self-Adaptive Single-Event Upsets Mitigation for Dependable Multiprocessing Systems”, Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019. [Gold Open Access]
  • (WP1 / IHP / ESR1.3) Nevin George, Michael Hübner and Heinrich T. Vierhaus, “From Fault Tolerance to Error Resilience: Co-Designing for Self Awareness”, Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • ... ESR1.4
  • (WP1 / IROC / ESR1.5, ESR2.3) T. Lange, A. Balakrishnan, D. Alexandrescu, M. Glorieux, and L. Sterpone, "Machine Learning To Tackle the Challenges of Transient and Soft Errors in Complex Circuits", Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • ... ESR2.1
  • ... ESR2.2
  • (WP1 / IROC /ESR2.3 / ESR1.5) Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu and Maksim Jenihhin “Modeling of a Gate-Level hierarchical abstraction using Graph Convolutional Neural Network - An explorational exploitation approach of Probabilistic Graphs for the prediction of functional derating”,Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • ... ESR2.4
  • (WP3 / IID / ESR3.1) Shayesteh Masoumian, Georgios Selimis, Roel Maes, Rui Wang, Geert-Jan Schrijen, Said Hamdioui and Mottaqiallah Taouil, “Analysis of SRAM PUF Stability in FinFET Technology”, Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • ... ESR3.2
  • (WP3 / TUD / ESR3.3) Troya Koylu, Cezar Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, “Machine Learning-Based Detection Model Against Fault Attacks for RSA”, Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • (WP4 / CDNS, TUD / ESR4.1, ESR4.2) Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer, "Combining Fault Analysis Tools for ISO26262 Functional Safety Verification," Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • (WP4 / CDNS, TUT / ESR4.2) C. Bagbaba, M. Jenihhin, J. Raik and C. Sauer, "Dynamic HDL Slicing Technique to speed-up the Fault Injection Campaigns," Proc. PhD Forum of the 9th BELAS Summer School, Frankfurt-Oder, Germany, June 10 - 12, 2019.
  • ... ESR4.3

 

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The RESCUE ETN project has received funding from the European Union’s Horizon 2020 Programme under the Marie Skłodowska-Curie actions for research, technological development and demonstration, under grant n. 722325.
RESCUE © 2017