ESR1.1 “Test and Reliability of FinFET memories”

Guilherme Cardoso Medeiros

Recruiting institution: Computer Engineering lab, Delft University of Technology, The Netherlands
Supervisors: Prof. Said Hamdioui, Prof. Mottaqiallah Taouil
Cross-sectoral co-supervisor: Dr. Dan Alexandrescu, IROC, France
Recruitment period: 22.11.2017 – 21.11.2020 (36 months)
PhD studies: Delft University of Technology 

ESR background

Guilherme C. Medeiros holds a BSc in Computer Engineering (2015) and a MSc in Electrical Engineering (2017), both from the Pontifical Catholic University of Rio Grande do Sul (Porto Alegre, RS, Brazil). During his bachelor studies, he also did an exchange period at Bucknell University (Lewisburg, PA, USA). He was an intern, and later a Master student, at the EASE lab. There, he worked with reliability of integrated circuits, focusing on memory circuits. His Master’s thesis emphasized on test of FinFET-based memories affected by manufacturing defects. His main research interests are FinFET SRAM defect modelling, and SRAM test and reliability. 

Individual research project 

TUD has already a well-established record in memory test and reliability research. The analysis in the IRP of RESCUE ESR1.1 will focus on FinFET memories using high-k material, which is a cutting edge technology and its comparison with the conventional plan CMOS memory technology. Although quite some work is done in the community with respect to FinFET memory reliability, almost nothing is known (at least in the public domain) on the FinFET memory testing. Appropriate electrical models of the FinFET memory defect mechanisms are missing, the complete space of fault models is not explored and validated yet, and finally, appropriate test algorithms and Design-for-testability are still missing.  This IRP aims at providing some solutions for these shortcomings.

The targeted objectives of this IRP are:

• Quantification of the quality and reliability characteristics of the defect and failure mechanisms.
• Quantification of the impact of quality and the reliability failure mechanisms on the functionality of the memory.
• Development of appropriate (defect and fault) models
• Development of appropriate test, DFX and/or mitigation solutions 

Intense collaboration will take place with iROC and Tallinn University of Technology. 

ESR1.2 “Adaptive methods for fault tolerant embedded systems”

Junchao Chen

Recruiting institution: Innovations for High Performance Microelectronics (IHP), Frankfurt-Oder, Germany
Supervisors: Prof. Milos Krstic, Prof. Peter Langendörfer (IHP and BTU CS)
Cross-sectoral co-supervisor: Prof. Heinrich Theodor Vierhaus, BTU CS, Germany 
Recruitment period: 01.02.2018 – 31.01.2021 (36 months)
PhD studies: Brandenburg University of Technology Cottbus-Senftenberg

ESR background

Junchao Chen was born on 17.09.1990 in Henan, China. He has studied the undergraduate studies at Polytechnic University of Turin (Italy) in Electronic Engineering from October 2011 to October 2014. He has continued the education and research in the field of the embedded system toward an M. Sc. degree at Polytechnic University of Turin in October 2014, and has finished it in December 2017. The previous experiences of embedded system gave him a strong background in programming, hardware developing and testing. Furthermore, with the experiences of two courses and one project related to testing and fault-tolerance during his Master’s degree, he has learned a lot of corresponding knowledge and skills. 

Individual research project 

Today’s embedded systems are susceptible to faults induced by the various sources. Radiation particles, voltage variations, crosstalk, technology defects etc. can affect the correct system operation. Due to technology scaling more and more complexity could be integrated into a single chip, and in the embedded applications the use of the multi-processor architectures starts to be the dominant trend. On the other hand, the increased design complexity and emerging technology issues are leading to even more pronounced challenges related to faults. Addressing faults is traditionally relevant for the reliability-critical applications, such as space and automotive, but nowadays becomes important even for the “mainstream” consumer applications. 

Traditional approaches for addressing faults include the static redundancy approaches in hardware, time, software, and/or information. The overhead, which such methods are imposing, is not acceptable for many applications. Moreover, today’s embedded systems are usually mixed-criticality systems, i.e. the requirements of the running applications with respect to safety, reliability, performance and power consumptions are dynamically changing in operation. As a consequence, the fault tolerance mechanisms could be applied more optimal in a dynamic adaptive way, reducing the overall power/performance overhead. 

This IRP has focused on exploring such adaptive use of the fault tolerance mechanisms in multi-core processing architectures, which are backbones of the modern embedded systems. The fault tolerant mechanisms should be synergistically addressed at different abstraction levels, including pipeline, block, processor and multi-processor system level. The goal is to enable and explore the dynamic trade-off between reliability, performance and power consumption in the relevant critical applications. This investigation will focus on adaptive cross-layer optimization approaches, taking into consideration different abstraction layers on the hardware side as well as the corresponding software stack and their mutual correlations.  Special attention will be paid to the dynamic use of extra hardware (needed for enabling an additional level of reliability or for increasing performance) and combination with the adaptive use of time redundancy methods. The proposed research activities include investigating and evaluating the methods for optimised task scheduling and adaptive mode switching in order to increase the lifetime of the target system and improve the overall energy consumption profile, while fulfilling the dynamically changing reliability requirements of the application.  

It is expected that this research activity will lead to the development of new methods beyond State of the Art, and that the corresponding results will be practically evaluated over test ASIC implementations and related measurements.

ESR1.3 “HW/SW fault tolerance methods driven by reliability and timing constraints”

Nevin George

Recruiting institution: Computer Science Institute, Computer Engineering Group, Brandenburg University of Technology Cottbus-Senftenberg, Germany
Supervisors: Prof. Heinrich Theodor Vierhaus, Prof. Michael Hübner
Cross-sectoral co-supervisor: Prof. Milos Krstic, IHP, Germany
Recruitment period: 01.04.2018 – 31.03.2021 (36 months)
PhD studies: Brandenburg University of Technology Cottbus-Senftenberg

ESR background

Previously George, Nevin was a developer and systems verification engineer at Stoneridge Electronics (Automotive Electronics Industry). He has received his Master’s degree in Computer and Systems Engineering, Cum Laude from TTU and his Bachelors in Computer Science and Engineering, First Class from University of Calicut, India. He has primarily worked with Fault-Tolerance and Dependability topics, in relation with Network on Chips during his Master years, and have contributed to the research which was towards development of an ASIC of the Bonfire project. During his research there he has co-authored a paper which was published at IEEE DDECS 2017. He has experience mainly in C, VHDL and many others such as Verilog, C++, Python, Java, Bash and Powershell Scripting, Matlab and also various operating systems such as Linux, Windows, Minix and Unix based Systems (Free BSD etc, MacOS) and so on. His main research interests are Computer Architecture, H/W and S/W interface, OS design, Reliability, Dependability and Fault tolerance designs; especially related to Fault Detection, Classification and Correction in digital circuits and systems, and so on. He has also had experience in Cyber Security and Industrial Experience in development and testing of S/W and H/W systems.

Individual research project 

The IRP is focused on methods for on-line error detection and correction in digital circuits, considering constraints in terms of power and timing. Essentially, the ESR has to analyse existing designs of error-correction circuits with respect to their applicability to real designs such as processor cores. Depending on timing and power constraints, either specific types of fault detection and correction circuits need to be applied, or such devices need to be designed to be configurable themselves in order to react on changing demands and constraints. For example, a processor may be used in a mode of “minimum timing and power” with error detection and correction left to software functions as one extreme, while it may be operated for fast on-line fault detection and correction at higher power and irregularities in timing on the other hand. Development of new concepts and architectures is done in close cooperation with IRP 2.2, which is targeted at the development of fault management concepts at the operating systems level. In total, the research work under way should achieve a significant step forward in the direction of “error resilient” system, which are capable of adjusting their inherent level of fault tolerance according to the application and their own internal fault status.

During the initial phase of the IRP, the ESR has to get an overview over concepts and designs for on-line test and fault correction on one hand and their applicability to real designs like processor cores on the other hand. 

Objectives for collaborative research:

• Analysis of existing architectural concepts for the detection and correction of delay faults and SET- or SEU-radiation induced faults
• Cooperation with ESR 1.2 at IHP
• Investigations on compatibility of such elements and their special features with real-life designs such as simple microprocessors
• Cooperation with ESR 2.2 at BTU 
• Development of fault detection elements that are optimized for configuration by OS system functions on one side and which allow to monitor fault events and circuit health status from OS-functions on the other hand.  
• Cooperation with ESR 1.2 at IHP and ESR 2.2 at BTU

The final overall objective is a scheme of flexible fault detection, optional correction and fault management for capabilities of “error resilience” at the system level which can adapt the system to changing demands in timing, fault correction and power dissipation.

ESR 1.4 “New Techniques for on-line fault detection”

Josie Esteban Rodriguez Condia

Recruiting institution: Department of Control and Computer Engineering, Politecnico di Torino, Italy
Supervisor: Prof. Matteo Sonza Reorda, Prof. Luca Sterpone
Cross-sectoral co-supervisor: Dr. Christian Sauer, Cadence, Germany
Recruitment period: 16.10.2017 – 15.10.2020 (36 months)
PhD studies: Politecnico di Torino

ESR Background

The ESR comes from Sogamoso, Boyaca, Colombia. He has a bachelor degree in electronics engineering (2013) from Universidad Pedagógica y Tecnológica de Colombia (UPTC). He then received a master’s degree in engineering with emphasis in electronics from the same university in 2017. He worked as adjunct lecturer by four years in this institution on subjects such as digital design, embedded systems and microprocessors architecture. He obtained a utility model patent as a part of his master thesis project. 

Individual research project

The IRP is focused on the development and evaluation of new techniques to check and verify the in-field correct operation of electronic systems, mainly complex modules corresponding to GPGPU (General Purpose Graphic Processing Unit) devices. The initial effort aimed at the development of methods to detect permanent faults arising during the operational phase, e.g., due to ageing phenomena. This activity is being accomplished by resorting to suitable Design for Testability (DfT) techniques and mechanisms, or to a functional approach, or to a clever combination of both. Other activities include the investigation on the impact of temporary faults, generated by external factors on the system, and the proposal of suitable techniques for detecting and tolerating them. The ESR will develop and evaluate different approaches combining solutions at different levels. 

Given the wide range of constraints existing in today application domains (e.g., in terms of cost, design time, performance, dependability, power), it is likely that the designer would need the flexibility of choosing the best trade-off for each single application. For this reason, it is crucial to own a deep knowledge of the available solutions, to be able to combine them into a unified framework, and to provide the designer guidelines about the parameters that need to be modified in order to achieve a given goal.

Activities will explore new challenges which are recently becoming important, e.g., on-line test of GPU-based systems, compaction of functional test programs, identification of functionally untestable faults, generation of rejuvenation stimuli.

The project will devise new approaches based on the existing solutions and taking into account the most significant constraints coming from industry. Test cases coming from industry will be identified and used first of all to evaluate the current solutions, and then to assess the effectiveness of the new ones. The final deliverable will correspond to a report detailing the proposed solutions and the results of their experimental evaluation.

The goal of this research action is to propose solutions able to significantly advance the state-of-the-art in the area of GPGPU-based systems for safety-critical applications.

The emphasis of the project will be put on GPGPU-based systems, specially focused on on-line test scenarios, due to their growing usage in safety-critical applications and High-Performance Centers with strict reliability and safety constraints. Hence, a deep and strong knowledge of the GPGPU architecture, control and management algorithms, and programming paradigms will also be owned at the end of the PhD program. Other objectives include a good knowledge and skills in compaction of functional test programs (SBST), the identification of functionally untestable faults (or safe) and the generation of rejuvenation stimuli facing the aging phenomena.

The main objectives for the collaborative research include:

• Analysis of the functional operation of a control and management module within a GPGPU in the presence of permanent faults. This module exists within the local schedulers of a GPGPU-based architecture and is crucial for the operation of the system. Development of functional test programs adopting the Software-Based Self-Test (SBST) approach in order to check the status of this controller, suitable to be used for in-field test in safety-critical applications. 
• Development and evaluation of on-line transient fault detection techniques for GPU-based systems.

ESR1.5 “Reliable operation infrastructure for dynamic, high-dependability applications”

Thomas Lange

Recruiting institution: IROC Technologies, France
Supervisors: Dr. Dan Alexandrescu, Dr. Maximilien Glorieux
Cross-sectoral co-supervisors: Prof. Matteo Sonza Reorda, Prof. Luca Sterpone, Politecnico di Torino, Italy
Recruitment period: 04.09.2017 – 03.09.2020 (36 months)
PhD studies: Politecnico di Torino

ESR background

Thomas Lange holds a Master of Science degree in Computer Engineering from TU Berlin. During his studies he specialized in Microelectronics, Computer Architecture and Signal Processing. From 2015 to 2017 he was a Young Graduate Trainee at the European Space Agency where he was working on the evaluation of a new radiation-hard SRAM-based FPGA for space applications (called BRAVE). In 2014/2015 Thomas was a student research assistant at TU Berlin and was responsible for the design and implementation of a magnetic-based absolute position sensor system in FPGAs. From 2011 to 2013 he was a student research assistant at Fraunhofer Heinrich Hertz and helped with the design and implementation of integrated digital circuits for embedded multimedia processing systems.

Individual research project

This ESR project will consider high reliability applications for aerospace, automotive, HPC that need to work reliably and safely in aggressive working environments. The researcher will propose error management techniques, methodologies and instruments to detect and/or correct errors and reconfigure the design to meet the environmental constraints. The project will focus mostly on hardware capabilities that will be transparent to the application or assisted by a light software layer. This activity targets novel tools, methodologies and nanoelectronic system IPs for the management (detection and/or correction) of multiple categories of faults induced by the environment, the application or the design itself. The research objectives include:

• Modelling, assessment and mitigation of transient faults (Soft Errors/Single Event Effects) in complex electronic devices such as CPUs, FPGA et memories
• Cooperation with PdT, TU Delft (ESR1.1)
• Development of test methodologies for complex electronic systems in aggressive
   working environments
• Cooperation with PdT (ESR1.4)
• Study, prototyping and benchmarking of reliability assessment methodologies and tools for the analysis of the impact of faults and errors on the function of complex systems used in high-reliability application; contributions to the zamiaCAD platform
• Cooperation with IHP (ESR1.2)
• Design hardening and improvement to improve functional reliability
• Cooperation with Cadence ESR4.1 (and ESR4.2)
• Design vulnerability analysis against radiation effects
• Cooperation with other ESRs supervised or co-supervised by IROC

ESR2.1 “Effective techniques for secure and reliable systems validation”

Aleksa Damljanovic

Recruiting institution: Dept. of Control and Computer Engineering, Politecnico di Torino, Italy
Supervisors: Prof. Giovanni Squillero, Prof. Matteo Sonza Reorda
Cross-sectoral supervisor: Dr. Dan Alexandrescu, IROC, France
Recruitment period: 16.10.2017-15.10.2020 (36 months)
PhD studies: Politecnico di Torino

ESR background 

Aleksa Damljanovic was enrolled as a student of Mathematical Grammar School in Belgrade from 2008 until 2012. He graduated in 2016 at the Department of Electronics, School of Electrical Engineering, University of Belgrade. Apart from being a master student at the same university in 2016/2017, Aleksa was doing an internship in a private company dealing with embedded design. Aleksa participated in Erasmus+ mobility program and was doing 6-month research in 2017 at the ETSII, Universidad Politecnica de Madrid, for the purpose of writing the master thesis: “Efficient FPGA SoC implementation of SVM face detection algorithm”. 

Individual research project

This ESR project is focused on developing new techniques able to support the designer of secure and reliable nanoelectronic systems in the validation of their correctness. In particular, the project will address the validation of mechanisms adopted by the designer to guarantee security and reliability. This task requires considering not only the space of all possible scenarios where the system is used, but also a further dimension represented by the possible hardware faults and external attacks the system is designed to face. Assessing the correct functionality of the system with such a huge combination of possibilities can only be done by combining different techniques coming from different communities (e.g., the one of software validation, the one of hardware validation, the one of hardware testing) and exploiting different paradigms (e.g., resorting to formal techniques, to evolutionary computation, to Design for Validation). The research objectives include:

• Proposal of new solutions for the validation of the correctness and effectiveness of the mechanisms implemented by the designers to face safety and security
• Sound research results for topics outlined in a); assessment of the effectiveness of the proposed solutions on some selected test cases.
• Prototypical environment implementing the proposed techniques (hopefully integrated into a commercial design flow platform), together with a report detailing the implemented techniques and the results of the performed evaluation experiments.
• Finding out about the state of the art in design, test and validation techniques tackling in particular reliability and security.
• Identification of the most relevant faults and attacks that have to be considered, together with some of the countermeasures used by the designers to face them; Identification of the requirements to validate their effectiveness and correctness.
• Working on the IEEE 1687 standard, with special emphasis on the reconfigurable scan network’s modules test time minimization.
• Identification of non-functional design constraints (such as malicious threats) for design functional validation
• Cooperation with TUT ESR2.4 

ESR2.2 “Innovative real-time operating system for error management for single- and multi-core units”

Raphael Segabinazzi Ferreira

Recruiting institution: Dept. of Distribute Systems / Operating Systems, Brandenburg University of Technology Cottbus-Senftenberg, Germany
Supervisors: Prof. Jörg Nolte, Prof. Heinrich Theodor Vierhaus and Prof. Michael Hübner
Cross-sectoral supervisor: Prof. Milos Krstic, IHP, Germany
Recruitment period: 01.10.2017 – 30.09.2020 (36 months)
PhD studies: Brandenburg University of Technology Cottbus-Senftenberg

ESR background

Raphael Segabinazzi Ferreira had his graduation in Electronic Engineering (2012) and his master’s in Electric Engineering with emphasis on Computer Systems (2016) from Pontifical Catholic University of Rio Grande do Sul (PUCRS). His master thesis topic was focused in security for processors and was developed under the supervision of Prof. Dr. Fabian Vargas. Also, at the same time, he worked since 2010 until half of 2017 as Embedded Developer on Research and Development (R&D) department of Brazilian companies. Now Raphael is currently a PhD student at Brandenburg University of Technology Cottbus-Senftenberg (BTU), campus Cottbus, Germany.

Individual research project 

Managing fault and error conditions in large-scale and distributed computer-based systems towards a pre-defined level of “error resilience” is by far an unsolved problem. Any possible solution will inevitably include methods and architectures for fault- and error detection and (optional) correction at the level of logic gates and RT-level functional blocks. Most of the previous work done in this area was at this level. The ultimate objective, however, is making such systems and their main components aware of their own status with respect to transient and permanent faults, but also with respect to the level of wear-out that system components may have reached. A layer of “self-awareness” in a complex system will not only monitor the actual status of health, but it may have to decide on necessary repair actions by i.e. triggering re-configuration of parts for built-in self-repair. Furthermore, computing resources need to be allocated for the control and monitoring or repair activities. The appropriate functionality for such high-level fault- and error management needs to be allocated in the operating systems of specific functional blocks, but possibly also in a higher OS-layer that can administrate a whole set of functional units. The project work to be performed here will take-up “low level” fault- and error information and use it for an optimized system-level error resilience at minimum cost. Development of new concepts and architectures is done in close cooperation with IRP 1.3, which is targeted at the development of fault tolerant units and management mechanisms at the processor and units level. The objectives for collaborative research include:

• Investigations on mechanisms for fault detection and correction according to their compatibility and special features with real-life designs such as simple microprocessors and OSes (cooperation with ESR 1.3 at BTU).
• Configuration by Operating systems functions of low level mechanism and fine-grained units at processor level, which allow the high level functions to monitor fault events, circuit health status and also perform system re-configuration according to necessity and the operational mode (cooperation with ESR 1.2 at IHP and ESR 1.3 at BTU).

ESR2.3 “A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability”

Aneesh Balakrishnan

Recruiting institution: IROC Technologies, France
Supervisors: Dr. Dan Alexandrescu, Dr. Maximilien Glorieux
Cross-sectoral co supervisor: Prof. Maksim Jenihhin, Tallinn UT, Estonia
Recruitment period: 03.01.2018 – 02.01.2021 (36 months)
PhD studies: Tallinn University of Technology

ESR background

Aneesh Balakrishnan has a master degree in Communication and Multimedia Engineering from Friedrich-Alexander University, Erlangen-Nurnberg, Germany in July 2016. During the period of two years, he worked as a student research assistant in speech coding department of International Audio Laboratory of Fraunhofer IIS, Erlangen. His bachelor degree is acquired in the area of Electronics and communication engineering from India. He has acquired a sound knowledge in digital signal processing, statistical signal processing, digital communications, speech and audio processing, image and video signal processing, convex optimization, signal analysis, pattern recognition, digital and embedded electronic design, linear integrated circuits, VLSI and also in programming languages such as C/C++, python, assembly language and MATLAB.

Individual research project

The ESR will address today’s high-performance designs requirements in term of validation and reliability. The project aims at developing an overall approach comprised of EDA modules and tools, design methodologies and testing practices for the modelling and management of the quality of complex design and systems. The objective of the research is to significantly enhance and develop new statistical, probabilistic methods and algorithm for TFIT (cell-level SER analysis) and SoCFIT (circuit-level reliability analysis) used in IROC tools. In addition to the software, EDA-based fault and error evaluation in complex designs, the project will also use and improve hardware fault injection (through radiation, laser testing, emulation) and failure analysis from field data.

The proposed research themes contribute towards the development of an industry-wide reliability framework and set of tools. The tool specifications will be established in collaboration with important companies from the networking and automotive applications. Test cases will be also provided by IROC industry and academy partners.

The objective of the research is to significantly enhance and develop new statistical, probabilistic methods and algorithm for cell-level and circuit-level reliability analysis and management. In addition to the software, EDA-based fault and error evaluation in complex designs. The project also planned to use and improve hardware fault injection and failure analysis from field data. The researcher will contribute to an exhaustive EDA platform for the modelling and management of the reliability of complex design and systems. The proposed ESR aims at contributing towards the development of an industry-wide reliability framework and set of tools.

The main aim of this research to investigate the uncertainties and failures in logic circuits, which generated by the soft errors. The new circuit and chip technologies are more vulnerable to the soft errors due to cosmic radiations, thermal energies and voltage scaling. In order to limit the exacerbation of the impact caused by soft errors in the logic circuits, a dedicated software tool is unconditionally required. However, when dealing with today's large complex circuits, traditional approaches such as accelerated fault simulation and other techniques require huge investment of time and resources. To overcome these drawbacks, the thesis is intended to propose fault propagation evaluation methods based on static and probabilistic methods.

The ESR shall possess extensive knowledge of the State-Of-The-Art and upcoming EDA methodologies, tools and frameworks for the reliability analysis of electronics. His expertise shall include:

• Static (probabilistic) and dynamic (simulation, fault injection) techniques and tools.
• Knowledge of current reliability-focused standards such as ISO26262 (automotive) or DO-254 (avionics); ability to lead the reliability assessment and the preparation of reliability reports and safety manuals for high-reliability designs and systems.
• Ability to propose logic models for any current or new types of faults and defects affecting microelectronic process, technology, standard cell libraries and complex designs. 
• Adding fault analysis and simulation features to sophisticated Design Validation Environments for today’s highly complex microelectronics circuits and systems.

ESR2.4 “Functional and non-functional verification and debug methods for complex nanoelectronic systems”

Xinhui (Anna) Lai

Recruiting institution: Dept. of Computer Systems, Tallinn University of Technology, Estonia
Supervisors: Prof. Maksim Jenihhin, Prof. Jaan Raik
Cross-sectoral co-supervisor: Dr. Dan Alexandrescu, IROC, France
Recruitment period: 20.11.2017 – 19.11.2020 (36 months)
PhD studies: Tallinn University of Technology

ESR background

Xinhui Lai received BSc and MSc degrees in Electronic Engineering from Politecnico di Torino, Italy, in October 2014 and April 2017 respectively. She has knowledge of digital electronics, microprocessor architectures, experience with FPGA technology as well as design synthesis. She has programming skills in VHDL, C, Java and script languages such as TCL. Her research interests include design, verification and testing of digital systems, EDA methodologies, design automation, embedded systems and hardware security.

Individual research project

The IRP is focused on design error functional verification and automated debug, i.e. localization and correction, as well as verification of extra-functional interdependent aspects in nanoelectronic system design such as security, reliability, power/performance envelopes, etc. As a part of the project, there will be considered complex HW representations at abstraction levels from Register Transfer Level (RTL) to Electronic System Level (ESL) as well as HW/SW interaction in the system. The objectives include ambiguity of multiple error validation/debug, scalability, complexity and practical usability of the automated approaches and analysis of fault propagation between abstraction levels and HW and SW components of the system. There will be developed modelling of individual non-functional aspects and will employ a multi-view aspect interference analysis approach. The developed methodology is planned to be integrated into open-source frameworks, and possibly into industrial EDA tool flows by companies involved into the RESCUE network.

The research project addresses non-functional design aspects in complex nanoelectronic systems designs and analytical evaluation of non-functional aspect induced design trade-offs. The short term-objectives for collaborative research of the IRP are as follows: 

• Analysis of the SOTA approaches for non-functional aspects verification. Preparation of a survey paper. Development of modelling for multi-view interference analysis of design aspects.
• Teamwork with other PhD students and postdocs at Tallinn UT.
• Identification of non-functional design constraints (such as malicious threats) for design functional validation
• Cooperation with POLITO ESR2.1 (and WP3 ESRs).  
• Development of Soft-Error Reliability (and Lifetime Reliability) evaluation and modelling approaches specific to target application domains. Development of a context-aware dynamic reliability concept.   
• Cooperation with iROC ESR2.3 (and ESR1.5)

ESR3.1 “Reliability analysis of SRAM based PUFs in Nano era”

Shayesteh Masoumian

Recruiting institution: Intrinsic ID, Eindhoven, The Netherlands
Supervisor: Dr. Georgios Selimis, Ir. Geert-Jan Schrijen 
Cross-sectoral supervisor: Prof. Said Hamdioui, TU Delft, The Netherlands
Recruitment period: 01.12.2017 – 30.11.2020 (36 months)
PhD studies: Delft University of Technology

ESR background

Shayesteh Masoumian, M.Sc. has a Master Degree in Electrical Engineering – Circuits and Systems from University of Tehran Under supervision of Professor Zain Navabi, (2014-2017). Her Master thesis is on the Design and implementation of a Network for Improving Performance in Distributed Processing and Memory Systems and she was a visiting Researcher at KTH – Royal Institute of Technology for 8 months under supervision of Prof. Ahmed Hemani (2016). She has an industrial experience on working for 8 months as hardware designer in Communication systems’ designing company in Iran (2013-2014). Her Bachelor Degree in Electrical Engineering - Digital Systems from Sharif University of Technology (2008-2012).

Individual research project

Security services need secure keys. In most of embedded systems, keys are stored in non-volatile memories or battery-backed SRAMs. This solution comes with the challenges of extra resources (dedicated chip), security vulnerabilities (tampering) and extra costs and liabilities (key provisioning by a third party). Silicon Physical Unclonable Functions (PUF) technology is a hardware security entity which uses local mismatch between circuit devices to produce secret keys. 

In this ESR project, fundamental research regarding Physical Unclonable Functions (PUF) technology and relating security primitives will be performed. Detailed investigation will be done regarding the reproducibility, uniqueness, reliability and security aspects of the technology. ESR should build background on security and cryptography, both theoretical and practical concepts. Also, ESR will work with tools and programming languages to simulate the designs and analyse data. 

In this ESR project, the impact of technology scaling on SRAM-PUFs will be investigated. For this purpose, new technologies which are used in industry (FinFET, FDSOI) are investigated. Reliability will be analysed and comparison with performance on previous technology nodes will be performed. Moreover, research and analysis on aging and variability on stability, uniqueness, and entropy will take place. Circuit level simulations are being performed, and ESR builds knowledge on new technologies’ parameters and their physical concepts. A model for PUF will be built and in case of access to real data, validation of the model with real data will be performed.

ESR3.2 “Design approaches for tamper resistant crypto implementations”

Dmytro Petryk

Recruiting institution: Innovations for High Performance Microelectronics (IHP), Frankfurt-Oder, Germany
Supervisor: Prof. Peter Langendörfer (IHP and BTU CS), Dr. Zoya Dyka
Cross-sectoral supervisor: Prof. Heinrich Theodor Vierhaus, BTU CS 
Recruitment period: 1.3.2018 – 28.2.2021 (36 months)
PhD studies: Brandenburg University of Technology Cottbus-Senftenberg

ESR background

Dmytro Petryk was born on 01.11.1993 in Kiev (Ukraine). He studied Radio engineering at Taras Shevchenko National University of Kiev from 09/2012 – 07/2015 receiving a Bachelor degree. He has continued the education and research in the field of Radio engineering pursuing a M. Sc. degree at the same university which he received –with distinction in July 2017. His background in physics as well as lectures attended in the field of system protection provide him with a solid background for successfully pursuing the research indented here.  He already published 7 papers in a conference series organized by his university. 

Individual research project

Wireless Sensor Networks (WSN) are used more and more in automation systems and in the area of critical infrastructure protection. One of the issues with WSN is that the devices can be stolen to attack them in a laboratory. One of the potential attacks that can reveal cryptographic keys are so called fault attacks. In these attacks faults are induced into an ASIC e.g. in order to get access to internal data.

Design and implementation of crypto hardware that is resilient against fault attacks is extremely sophisticated, if not impossible. At least, currently, there are no guidelines how to do it. The core idea here is to prevent manipulation of cryptographic devices by using e.g. laser-based attacks. The ESR project will develop a solution to use different ways to implement cipher algorithms. This will be achieved by using variants of the operations or by using different types of gates. These and potentially other alternatives will be carefully evaluated. The results will provide guidelines for implementing more fault resilient cryptographic algorithms.

The main research result expected is the evaluation of different ways to improve the resilience against fault attacks. Based on that evaluation general principles for making hardware resistant against fault attacks will be synthesised. In order to achieve this, different versions of cryptographic devices will be realised to provide the basis for experiments. ECC and AES hardware accelerators will be implemented and manufactured in the IHP technology using the methods mentioned above. The research objectives include:

• Analysis of state of the art as a basis for definition of models for fault injection attacks. 
• Set-up of equipment and getting hands-on-experience running fault injection attacks as a basis for evaluation of research results in later stages
• Modelling fault injection attacks based on fault models normally used for reliability issues
• design of countermeasures against fault injection attacks 
• development of design guidelines that help to prevent fault injection attacks
• Evaluation of the design guidelines.

Exploration of all or set of proposed research objectives would create potential for significant impact of the research results.

ESR3.3 “Intelligent Hardware Design for Fault Attack Mitigation”

Troya Cagil Koylu

Recruiting institution: Computer Engineering lab, Delft University of Technology, The Netherlands
Supervisor: Prof. Said Hamdioui, Prof. Mottaqiallah Taouil 
Cross-sectoral supervisor: Dr. Georgios Selimis, Intrinsic ID, The Netherlands
Recruitment period: 15.01.2018 – 14.01.2021 (36 months)
PhD studies: Delft University of Technology

ESR background

Troya Cagil Koylu, born in 06.06.1992 – Canakkale/Turkey, is currently a PhD candidate in Computer Engineering, TU Delft. He achieved his bachelor (with honorary standing) in Electrical and Electronics Engineering and masters in Computer Engineering, both in Bilkent University. His research experience consists of Deep Learning, namely, image segmentation using deep learning and secure implementation of Convolutional Neural Networks. 

Individual research project

The analysis of the IRP of RESCUE ESR3.3 will focus on the development of intelligent hardware design for the detection and mitigation of fault injection attacks. Introducing faults to a system deliberately can result in leakage of secret information. Although there are many fault and fault attack mitigation techniques in the literature, constant improvement in the state of the attacks make it necessary to develop novel and long lasting mitigation techniques. Potentially, introduction of AI and machine learning tools to hardware design can help to attain such mitigation techniques. This IRP aims to develop such solutions, with the help of the established knowledge in hardware security, in TUD.  

The targeted objectives of this IRP are:

• Design of intelligent detectors in hardware, for fault attack detection.
• Exploration and development of AI and machine learning methods to be used as hardware detectors.
• Analysis and modelling of the existing hardware (and if needed, related software) attacks, especially fault injection attacks.

Intense collaboration will take place with Intrinstic ID.

ESR4.1 “EDA tools and methodologies for reliable nanoelectronic systems”

Felipe Augusto da Silva

Recruiting institution: Cadence Design Systems GmbH, Munich, Germany
Supervisor: Dr. Christian Sauer
Cross-sectoral supervisor: Prof. Said Hamdoui, TU Delft, The Netherlands
Recruitment period: 30.10.2017 – 29.10.2020 (36 months)
PhD studies: Delft University of Technology

ESR background

The ESR holds degrees as Bachelor of Science (BS) in Computer Engineering and Master of Science (MSc) in Electrical and Electronics Engineering, from Pontifical Catholic University of Rio Grande do Sul (PUCRS) and Federal University of Santa Catarina (UFSC), respectively. During his academic career, the ESR has worked on researches concerning the effects of radiation effects aiming FPGA-based On Board Computers for artificial Satellites. In addition, the ESR has 6 years of experience working in the Aeronautics and Defense industry as an embedded software developer.

Individual research project

The research project will focus on the functional safety aspect of nanoelectronic systems design. The PhD Candidate will be integrated with the Cadence functional verification field engineering group, aiming to demonstrate the usage of fault injection techniques to assess functional safety at different stages of the design flow, focusing on the correlation of the faults in Virtual Platforms to faults at lower abstraction levels. The PhD candidate will employ state-of-the-art approaches that allow using Virtual Platforms to expose design areas more sensitive to various kinds of failures. Additionally, the effect of the failures on the Virtual Platforms will be used to propose techniques to allow improvement of the fault injection campaign duration. 

The PhD candidate will explore the following areas: 

• dependability concepts, fault modelling and reliability analysis correlation between Virtual Platforms and lower abstraction levels of hardware design flow; 
• automate design scrutiny for sensitivity spots to single event effects aiming design reliability during life-time; 
• static and dynamic analysis of injected faults using statistics to increase design confidence;  
• study the performance contribution of different techniques targeting faster fault injection campaigns; 
• integrate reliability analysis into automated flows of proven methodologies like metric driven verification; 
• investigate fault collapsing solutions to optimize fault injection at different abstraction and integration level.
• define characteristics of automotive digital designs and benchmarks to allow proper selection of designs to verify the proposed techniques and methodologies.

PhD candidate will implement this project through state-of-the-art exploration and proposal of new solutions to design for reliability and verification; study of safety standards for electronic systems like ISO26262; study of internal and customer test cases; contribution to writing of material such as application notes and white papers.

ESR4.2 “EDA Tools and methodologies for high quality nanoelectronics systems”

Ahmet Cagri Bagbaba

Recruiting institution: Cadence Design Systems GmbH, Munich, Germany
Supervisor: Dr. Christian Sauer
Cross-sectoral supervisor: Prof. Maksim Jenihhin, Tallinn UT, Estonia
Recruitment period: 04.12.2017 – 03.12.2020 (36 months)
PhD studies: Tallinn University of Technology

ESR background

Ahmet Cagri Bagbaba obtained his B.Sc. and M.Sc. degrees in Electronics and Communication Engineering from Istanbul Technical University in 2013 and 2015 respectively. From 2014 to 2017, he was a research assistant at the same university and worked on digital ASIC/FPGA design and verification. During this work, he published papers along with assisting digital design courses. In 2017, he was with IMEC in Leuven, Belgium as an ASIC physical design engineer on their high-tech chip implementation projects. 

Individual research project

This research project will focus on the functional safety aspect of nanoelectronic systems design. The PhD candidate will be integrated with the Cadence functional verification field engineering group. The PhD candidate will demonstrate the usage of fault injection techniques to assess functional safety figures at different stages of the design flow and improved modelling of fault tolerant designs. The PhD candidate will employ state-of-the-art approaches that allow exposing design areas more sensitive to various kinds of failures.  Moreover, the research aims to change the paradigm of circuit design and design automation to enable reliable system. The program provides techniques for state of art and future technologies, ranging from technology modelling, fault detections and analysis, circuit hardening, and reliability management. Additionally, the PhD candidate will present proposed solutions to automate EDA tool flow in order to analyse design reliability and optimise the compliance process to latest safety standards. 

The PhD candidate will explore the following areas:  

• dependability concepts, fault modelling and reliability analysis across different moments of hardware design flow; 
• investigate fault collapsing solutions to optimize fault injection at different abstraction and integration level.
• designing of fault tolerant hardware and then improving analysis techniques to capture their impact on design performance and functionality better;
• finding new fault tolerant design methods together with improved fault injection methods;
• automate design scrutiny for sensitivity spots to single event effects aiming design reliability during life-time; 
• safety analysis of designs with different fault tolerant and resilience mechanisms; 
• usage of dynamic simulation, formal and emulation techniques focusing on safety verification; 
• static and dynamic analysis of injected faults using statistics to increase design confidence;  
• study the performance contribution of emulation to other techniques targeting faster fault injection campaigns; 
• integrate reliability analysis into automated flows of proven methodologies like metric driven verification; 

The PhD Candidate will implement this project through state-of-the-art exploration and proposal of new solutions to design for reliability and verification; study of safety standards for electronic systems like ISO26262; study of internal and customer test cases; contribution to writing of material such as application notes and white papers.

ESR4.3 “Open-source EDA tools for design quality and reliability automation”

Cemil Cem Gürsoy

Recruiting institution: Dept. of Computer Systems, Tallinn University of Technology, Estonia
Supervisor: Prof. Maksim Jenihhin, Prof. Jaan Raik
Cross-sectoral supervisor: Dr. Christian Sauer, Cadence, Germany
Recruitment period: 24.11.2017 – 23.11.2020 (36 months)
PhD studies: Tallinn University of Technology

ESR background

Cemil Cem Gürsoy has a MSc degree in Computer Engineering and BSc degree in Electrical and Electronics Engineering from Yeditepe University, Turkey. He is confident in C, C++, Java, Perl, PHP, Python and MatLab programming languages and Verilog, VHDL HDLs. He worked two years as a research assistant and six months as an FPGA engineer, where he gained experience on digital design with HDLs, EDA tools, embedded systems, testing, DFT and co-authored three papers on these topics. His research interests are design, verification and testing of digital systems, BIST, DFT, EDA methodologies, design automation, embedded systems and hardware security.

Individual research project

The IRP is focused on EDA (Electronic Design Automation) methodologies and development of EDA tools for design quality and reliability in nanoelectronic systems with a focus on processors or multi-processor SoCs. The project will exploit an open-source platform zamiaCAD with a frontend for RTL (Register-Transfer Level) descriptions and a scalable internal model. This platform has already successfully served as a basis for applications such as design error verification and debug as well as NBTI (Negative-Bias Temperature Instability) ageing modelling and development of mitigation techniques. The tools developed within this project are expected to be kept open source and easily accessible to the community. At the same time, they will highly respect state-of-the-art industrial requirements and practices (e.g. scalability, formats and standards). As the result, there will be developed novel approaches for functional validation, fault tolerance/resilience mechanisms and static and dynamic analysis of reliability threats (ageing, radiation-induced errors, etc.) at RTL as well as their automation.

Up-to-date EDA tools and methodologies for complex (large, processor-based, heterogeneous, many-core) nanoelectronic systems design automation respecting the trade-offs and enhancing design aspects such as reliability, security, quality, power-performance.

Objectives for collaborative research:

• Build a reliability and quality analysis experimental environment based on zamiaCAD tool and a case study composed of an open-source NoC platform Bonfire (RTL VHDL) with open-source Plasma MIPS processors. 
• Potential collaboration with several ESRs.
• Modelling, assessment and mitigation of ageing in processor memories
• Cooperation with TU Delft including ESR1.1.
• Design reliability for application specific requirements (e.g. automotive) and fault injection techniques. 
• Cooperation with Cadence ESR4.1 (and ESR4.2).
• Design vulnerability analysis against radiation effects
• Cooperation with IROC ESR1.5 and ESR2.3.